Phase Interpolator, Cadence tool experience, CAD tools for circuit simulation, CMOS design, Bias and Bandgap Voltage Regulators, SERDES, jitter and signal equalization techniques, High Speed Clock Distribution, Low jitter PLL, layout and physical verification

Phase Interpolator, CAD tools for circuit simulation, CMOS design, Bias and Bandgap Voltage Regulators, SERDES, jitter and signal equalization techniques, High Speed Clock Distribution, Low jitter PLL, layout and physical verification

Logic Design, DDR, AMS verification, system level design, Mixed Signal IP design, AMS design techniques, High-speed circuits, Lab debugs on AMS IPs, Tx Rx CTLE Amplifiers Samplers, Analog Mixed Signal design, HBM technologies, Circuit architecture, SERDES

Physical Design Verification, Calibre, FinFET designs, DRC, ESD coverage techniques, Antenna Density Fill Routines, LVS, Dfm, XOR, DFM techniques, Siemens tools