Eda, Machine Learning, Artificial Intelligence, automation, physical implementation, extraction and simulation workflows, generative AI, design migration and design reuse, analog and custom IC design, LVS, OpenAccess-based design environments, semiconductor design, Physical Verification, circuit simulation SPICE, DRC, Parasitic Extraction, analog verification flows, standard cell design and optimization, Cadence Virtuoso

Static Timing Analysis, Tcl, Python, Perl, Scripting Languages, routing, physical design flow, physical design constraints, Cadence Innovus, debug skills, Cadence Genus, EDA Tools, Cadence Cerebrus, IC design, clock placement, Timing, Power