Git, Bitbucket, Verilog, Visualstudio, Python, System C, Uvm, systemverilog

static timing analysis, EDA tools for synthesis, VHDL, verification methodologies, RTL design using Verilog, clocking resets, Simulation, Timing Analysis, low-power design techniques, digital IC ASIC design, RTL quality tools such as Spyglass Lint CDC RDC

arm architecture , C, Usb, DDR, Pcie, Perl, Ethernet, Tcl, hardware emulation support, TLMs in SystemC, Uvm, eMMC, assertion-based formal verification tools

C, Embedded Software Development, RS232 communications protocols, Iso 13485, IEC 62304, ARM AVR processor development, Sensor sampling, IEC 60601, Intel embedded X86 development, FPGA programming, Embedded RTOS development, ARM processor development, Linux development environment, IEC 62366, Assembly

regulators , Verilog, Matlab, IC design CAD tools, RF and Analog Design, Mixed signal circuits, TX, Bandgap bias circuits, RX, Spice, ADCs, Silicon Germanium SiGe BiCMOS, Spectre, Pll, DACs, HSIM, Filters, Bipolar Complementary Metal Oxide Semiconductor technology

Shell, Pcie, Perl, Arm, Python, Tcl, MCU, AMBA, Axi, UCIe, systemverilog