Vcs, shell scripting, Static Timing Analysis, Python, Tcl Scripting, Lsf, AI ML, Object Oriented Programming, Linux, Perl, Virtuoso-L, Xcelium, Quantus, Cadence custom IC Virtuoso, parasitic extraction tools, StarRC, Synopsys custom compiler, Primesim, EM IR STA, Finesim, analog circuit simulation flows, Virtuoso-XL, XA, Cadence language, circuit simulation debugging, Spectre, CMOS concepts

Tcl, Python, Perl, Synopsys Design Compiler, primetime, Tempus, Cadence Genus, Logic Synthesis, low-power design techniques

Logic Design, Unit Testing, Backend, Synthesis, high speed design, LINT, ASIC design flow, Equivalence Check, cdc, Verification, Sta, ASIC synthesis constraints, Timing, Digital design concepts, Power estimation tools, IP level verification, Functional safety design, Front end implementation tools, Gate level simulations