Schematic design, Altium Designer, Production data releases, EMC optimizations, Siemens Xpedition, Electrical hardware design, Pcb Layout, Thermal concept, component selection, Automotive and functional safety development processes, design for manufacturing, Low voltage power electronics design, Design to Cost

hierarchical layout techniques, 3nm technology, custom layout design, Mentor Graphics Calibre, Totem tools, Cadence Innovus, device matching, Cadence XL, designing custom analog blocks, full-chip integration, IR drop analysis, low-parasitic layout practices

IR drop, Calibre, Cadence Virtuoso XL, PEX, CMOS IC mask design, DRC, device and signal matching, LVS, electromigration, coupling capacitance

Phase Interpolator, CAD tools for circuit simulation, CMOS design, Bias and Bandgap Voltage Regulators, SERDES, jitter and signal equalization techniques, High Speed Clock Distribution, Low jitter PLL, layout and physical verification

Phase Interpolator, CAD tools for circuit simulation, CMOS design, Bias and Bandgap Voltage Regulators, SERDES, jitter and signal equalization techniques, High Speed Clock Distribution, Low jitter PLL, layout and physical verification

vehicle safety , control panel design , wiring diagrams , Autocad Electrical, HVDC components, Functional safety, Cable harness design, Inverters, Electrical System Design, Electrical schematics, Relays, CAN bus layout, Layout drawings, DC-DC converters, Teamcenter

Pcie, Multilayer PCB designs, SerDes signals, DDRx, PCB layout concepts, High-Speed PCB Design, Complex PCB Design, High-speed routing techniques

PERL, Python, Tcl, Ir, Mentor, Cadence, LVS, EM Signoff, Synthesis, Formal Equivalence, DRC, Synopsys

Github, Sql, Shell scripting, Grafana, Ldap, Lsf, Tcl, Python, Perl, Jenkins, Gnu Make, Git, EDA Tools, Mentor Calibre, Synopsys VCS, Sungrid UGE, Cadence Virtuoso

test mode timing constraints definition, DFTMax, Cadence Encounter Test, simulating test vectors, Transition delay test coverage analysis, ASIC DFT, Genus Synopsys, TetraMax, equivalence check DFT DRC rules, DFT concepts, timing fixes, Scan Insertion, ATPG coverage analysis