Title: Standard Cell P&R Engineer

About GlobalFoundries

GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world's most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com.

Introduction

In this position you will be integrated in our Foundry IP Development team in Bangalore. In close collaboration with other disciplines across our worldwide engineering teams you will be developing layout for Std cell IP which enables our customers to perform product designs at highest quality standards based on GlobalFoundries advanced process nodes.

Job Responsibilities

Development of product grade Standard Cell IP covering PPA Benchmarking and validation of physical abstract views.
Run various stages of physical design flow to validate standard cell library physical abstract views (FRAM, LEF, NDM) using multiple EDA tools.
Validate Pins accessibility and routability of standard cells by pushing the routing density in P&R iterations in a congestion driven design.
Run Calibre DRC & LVS checks on routed database and sign-off for Library release.
Perform Benchmarking runs on multiple designs to provide PPA projection and comparison reports across various process nodes and Libraries.
Collaborate with standard cell design and layout engineer in Library Architecture analysis by performing early PPA evaluation.
Implement innovative solutions in the Standard Cell domain which are in line with GlobalFoundries's business needs.
Being a good team player, taking key initiatives for productivity improvements and innovation.
Sign off and release into dedicated IP validation test chips.

Required Qualifications

Education MS/M-Tech in Electrical/Electronics Engineering with 10 years of relevant Experience PhD (Electronics/Electrical/VLSI etc. with 6 years of relevant Experience)
Relevant hands-on experience in standard cell library P&R validation.
Should have worked on Standard cells libraries for various process nodes especially deep Submicron, FinFET and SOI. Exposure to chip-level scenarios is a plus.
Proficient in handling EDA tools from Synopsys, Mentor and Cadence used for Synthesis, P&R, STA.
Basic understanding of Standard Cell Layout Design and Layout Architecture.
Basic understanding of fabrication steps and flow.

Preferred Qualifications

Programming experience applicable to design flow automation tasks.
Industry standard flow methodology development experience is a plus.
Experience in Testchip integration and analysis will be an added advantage.
You are flexible, highly motivated and have a team-oriented working style.
You have shown the ability to communicate as well as work efficiently in an international multi-disciplinary environment.
Strong written and verbal communication skills in English are a must.

GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency and innovation whilst our employees feel truly respected, valued and heard. As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities. All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations.

Information about our benefits you can find here: https://gf.com/about-us/careers/opportunities-asia

Standard Cell PnR Engineer

Design Engineer- PNR/STA