Dsp, C, Debugging, Verilog, System Verilog, Systemc, Gate-Level Simulation, Power aware verification, Uvm, Assertions, Asic Design Verification, NPU, Processor Architecture, formal verification, HVL, Digital Design, Assembly

C, Ovm, virtualization, Perl, Python, Tcl, Client Server centric CPU features, SystemVerilog Assertions, cache controllers, x86 assembly, semi randomized test generators, FPGA HW platforms, Uvm, systemverilog, Validation using Emulation, validation strategy development, memory coherency, debugging test failures, power management, coverage driven Validation methodologies

systemverilog, Uvm, Verification Planning, Testbench Development, Debugging Skills, Functional Coverage