Ml, Perl, Python, Tcl, regression management, AMS Co-Simulation, Ai, mixed-signal verification, simulation coverage analysis, Uvm, systemverilog

Fpga, Tcl Scripting, FPGA hardware platforms

Uart, Spi, Perl, Verilog, I2c, Python, Tcl, Synthesis, cdc, Timing Analysis, AMBA protocols, digital IP development, systemverilog, Rtl Design, RDC, EDA Tools, DMA, low-power design concepts

Perl, Python, Tcl, constraint generation, Clock Tree Implementation Techniques, Rtl Design, Synthesis, STA using Primetime, Physical Verification, UPF CPF definition, Timing Closure, Power Estimation, ASIC Design, Low Power Power Analysis, Validation, formal verification, Place and Route Implementation

Digital logic design using FPGAs, Debugging and problem-solving skills, Timing Closure, Verilog RTL design, Timing Analysis, FPGA Design Flow

C, System Verilog, IP verification, Uvm

Tcl Scripting, Vivado Quartus or Libero Tools, RTL Design using Verilog VHDL, Hardware Debugging and Board Bring-up, FPGA Design Flow Synthesis Implementation P R Timing Closure, High-Speed Protocols PCIe Ethernet DDR Transceivers, FPGA Design and Validation, CDC Clock Domain Crossing Analysis, Simulation using Questasim, FPGA Integration Experience, Experience using Oscilloscopes and Logic Analyzers, Static Timing Analysis STA