CPF UPF formats, Digital timing concepts, DFT concepts, Digital circuit design, power analysis, Functional simulation tools, coverage analysis, AMBA protocols, Synthesis tools, Timing Closure, spyglass, Design For Testability, RTL Coding, Lint and CDC analysis, SoC clock architecture, ARM based SoC architecture

static timing analysis, Verilog, Synthesis, Simulation, formal verification tools, multi-power-domain design techniques, Uvm, systemverilog, Synopsys Spyglass, VHDL, Siemens Questa Formal, digital design flow, FPGA design methodologies

power optimization , Verification Methodologies, Mixed-Signal Integration, Timing Closure, Digital Circuit Design, Digital Architecture

power supply , Fpga, Analog, Emc, Spi, Emi, Digital Design, Aerospace, Simulation, Product Design

Fpga, Matlab, ASIC, VHDL, Simulink

Scripting Languages, Verilog, microcontroller and Flash Controller architectures, systemverilog, collaborating with analog teams on mixed-signal data paths, functional safety mechanisms, automotive software development, lint and CDC analysis, silicon bring-up and debug, Synthesis, Timing Closure, safety architectures for MCUs SoCs and automotive ECUs, Embedded Systems, Dft, Hardware Design, RTL-to-GDSII design flows

boundary scan , DFT techniques, scan design, industry-standard DFT tools, ATE platforms, low-power DFT methodologies, MBIST, UPF, IP integration, production test environments, hierarchical DFT approaches, ATPG, power domain testing, LBIST, CPF, Compression