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Showing 4 jobs
Skills:
static timing analysis, Perl, Verilog, Python, Tcl, Rtl Design, Synthesis, Dft, ATPG, systemverilog
Skills:
static timing analysis, Synthesis, multi-power-domain design techniques, Simulation, Uvm, FPGA design methodologies, formal verification tools such as Siemens Questa Formal and Synopsys Spyglass
Skills:
Perl, Python, Tcl, Xcelium simulation, vManager, Real-Number Modeling, Verilog-AMS, JasperGold, Uvm, SVA, systemverilog
Skills:
Version Control Systems, Tcl, Verilog, static timing analysis, Perl, Git, Shell, Perforce, Python, Scripting Languages, AHB, LEC, systemverilog, EDA Tools, LINT, Rtl Design, Synthesis, APB, Axi, SoC Architecture Design, SoC Integration, cdc, formal verification, AMBA protocols, Simulation
