Tcl, Python, Perl, RTL to GDSII, LVF POCV variation formats, Constraint Generation, STA Static Timing Analysis, Cadence Tools, Tweaker Prime Time, Automation scripts, Timing ECO Implementation, Timing Closure, Timing Analysis, Digital design Implementation

design optimization, Logic Synthesis, Physical-aware RTL-to-gate synthesis, CDC-related timing issues, Timing Closure, PPA optimization, Post-route timing analysis, Formal equivalence checking, SDC constraints, ECO implementation, MMMC timing analysis