Perl, Python, Tcl, Automation scripts, LVF POCV variation formats, STA Static Timing Analysis, Timing ECO Implementation, Constraint Generation, Synopsys Cadence tools, Digital design Implementation RTL to GDSII

Perl, Python, Tcl, Logic Synthesis, Physical-Aware Synthesis, PPA optimization, UPF management, Low-Power Implementation, systemverilog

Static timing analysis, design optimization, SDC constraints, Logic Synthesis, Timing ECOs, Clock-gating checks, CDC-related timing issues, UPF, ECO implementation, MMMC timing analysis, Timing Closure, Formal equivalence checking, CPF, Low-power design methodologies, PPA optimization, Physical-aware RTL-to-gate synthesis