Dsp, C, Debugging, Verilog, System Verilog, Systemc, Gate-Level Simulation, Power aware verification, Uvm, Assertions, Asic Design Verification, NPU, Processor Architecture, formal verification, HVL, Digital Design, Assembly

Bash, Pcie, Perl, Python, Tcl, CHI, Ace, Uvm, systemverilog, Axi

Vcs, programming, System Verilog, Scripting, Python, Asic verification, NCSim, verification of HBM memory interfaces, UVM testbench development, verification of SerDes IP block interfaces, Modelsim, formal model equivalence checking