Usb, Perl, Verilog, Sata, Python, DV methodologies, PCI Express, Uvm, systemverilog, VMM, constrained random verification, functional coverage

PCIe Formal Verification Engineer, PCI Express, formal verification, FPV, SVA, SystemVerilog Assertions, Questa Formal

C, Perl, Verilog, Python, Tcl, VHDL, Uvm, systemverilog

Constrained-random testing, SoC Verification, Coverage-driven verification, systemverilog

C, Software Development Life Cycle, Data Analytics, Python, Protocol analyzers, IO tools, Debugging tools for Embedded Systems, Embedded system concepts and architecture, Github Copilot, Ai, ML models