Usb, Perl, Verilog, Sata, Python, VMM, PCI Express, Uvm, systemverilog

Unix, Git, Linux, Perl, Verilog, Ovm, Python, VHDL, Uvm, systemverilog

AI ML accelerators, systemverilog, vector processing units, functional coverage

reusable testbenches, traffic generation, UVM methodology, verification planning, debugging skills, scalable verification environments, debug infrastructure, systemverilog, coverage models, SVA SystemVerilog Assertions

Shell, Perl, Vcs, Python, Xcelium, Questa, Uvm, systemverilog, SVA

code coverage , C, Shell, Perl, Verilog, System Verilog, Python, Tcl, Metric Driven Verification, Uvm, formal verification methodologies, assertions, functional coverage, constrained random methodologies