protocol stack , Java, Gerrit, Bash, Jenkins, Git, Qos, Python, Lte, Linux environments, latency, air-interface technologies, QoE, CI CD, system-level verification, resource load, KPIs, 5G NR, Troubleshooting, RAN architecture, throughput, ip networking

Verilog, Oops Concepts, scripting and tool development using Perl, VCS or equivalent simulation tools, debug tools like Debussy GDB, VMM, Uvm, systemverilog

Keysight, Exercisers, LeCroy, PIPE Interface verification, Uvm, PCIe Protocol Gen5, systemverilog, Protocol Analyzers

Noc, C, Pcie, Perl, Python, Reset and power verification, SOC verification methodologies, SOC bring-up, Uvm, Post-silicon verification, Axi, HW FW interaction verification, Coherency verification, Bus Fabric, AHB, UPF integration

simvision , Cadence Tools, SV UVM-based mixed-signal testbench development, Xcelium, VIVA, Behavioral modeling using SV-RNM Verilog-AMS, SoC-AMS testbench development, Virtuoso ADE, Assembler

code coverage , Python, C, Debugging, Shell, Tcl, Verilog, System Verilog, Perl, Uvm, constrained random methodologies, Metric Driven Verification, assertions, functional coverage, formal verification methodologies

Computer Architecture, Perl, Debugging, Python, Formal Verification methodologies, IP SOC verification, Functional Verification, Uvm, systemverilog, Rtl Design

Shell, Perl, Python, formal property verification, complexity reduction techniques, formal verification technologies, formal testbenches, testplans

Shell, Python, Perl, Scripting Languages, DACs, Uvm, SV, Dms, behavioral modeling, Signal Processing, digital RTL, ADC, Synopsys VCS, Analog Mixed Signal, DV, full chip verification, Cadence Virtuoso, verification plan, Oscillators, Pll, Debug