Shell, Perl, Vcs, Gdb, Python, System Verilog, Asic verification, RTL, Debussy, Uvm

Test Plans, Nvme, DDR, Pcie, coverage analysis, UVM methodology, systemverilog, Axi, RTL debugging, testbenches, assertions, AHB

DDR, Pcie, System Verilog, verification methodologies, quality metrics, Uvm, NAND, ASIC simulation tools

Database Management, System Verilog, silicon debug, AI-Tools, Simulation Tools, Cadence, verification management tools, formal property checking tools, assertion-based verification, Uvm, gate-level simulation, debug environments, Synopsys VCS, formal verification, power-aware verification, Synopsys JasperGold, VC Formal

Makefile, Windows, Perl, Linux, Python, IP-level ASIC verification, simulation profiling, UVM methodology, UVM testbenches, systemverilog, formal verification, testbenches, Efficiency Improvement, UVM-based verification frameworks