System Verilog, Python, Tcl, RTL synthesis tool development, UPF, parallel algorithms, formal verification, Dft, VHDL, RTL gate level logic optimizations, RTL synthesis technology, RTL design IP development, power synthesis, logic optimizations, Dynamic Power

Python, HTML, api documentation, Ms Word, Technical Writing

Virtual Networking, Network-as-a-Service

Python Scripting, Ims, Docker, Linux, Unix Os, Kubernetes, AWS, PCSCF, Testing IMS core products, Volte, SIP

Oracle Cloud Infrastructure, firewall rules, IAM Deny policies, Zero-trust Packet Routing, Security Zones