Multi-voltage domains, Physical design methodologies, Physical Verification, Power gating, PDN IR signoff, ASIC design flows, DDR PD expertise, 3DIC, Physical Design, Bump Spec understanding, RDL-design, PPA optimization, PCIE-high speed interface

Perl, Python, Tcl, Clock domain partitioning, Power integrity and power-aware physical implementation, Block and subsystem-level physical design flows, primetime, Fusion Compiler, Clock gating, Congestion analysis and resolution, Clock tree architecture, Tempus, Cadence Innovus, Skew management, Certus, Synopsys ICC2, Timing closure and constraint management

Tcl, Python, Perl, routing, floorplanning, UPF, RTL-to-GDSII execution, Physical Verification, automated design methodologies, LVS closure methodologies, Ir, Placement, CTS, signoff, Sta, low-power design strategies, ECO flows, physical signoff, CPF, Synthesis, Si, EM analysis, DRC

power integrity , Pvs, Static Timing Analysis, Python, Tcl, primetime, ICC2, Cadence Innovus, Synopsys Fusion Compiler, LVS, Dfm, Calibre, Physical Verification, StarRC, UCIe PHY Integration, Antenna, floorplanning, EM, IR-drop, Place-and-Route, Thermal-aware Placement, Physical Design, ERC, Timing Closure, DRC

IR EM Analysis, SI PI Analysis, Physical Verification, Floorplanning and Power Planning, Low Power Design UPF CPF, STA and Timing Closure, Physical Design and Signoff, Tcl Python Scripting, Clock Architecture and CTS, Advanced Node Design Methodologies, AI-assisted Design Flows

Perl Scripting, Sta, High Speed Cores, Circuit Level Comprehension, RTL to GDSII Implementation, Signal Integrity, Leakage Power, Multi-Vt Flow, Dfm, IC design, Power Supply Management, Deep Sub-Micron Design Problems, Physical Design, Power Gating, High Frequency Design Convergence, PDN Methodology, PPA Targets, Timing Signoff

Machine Learning, Eda, Automation, Shell, Perl, Python, Tcl, CAD, Ai, RTL-to-GDSII flows, Physical Design, EDA Tools, Silicon Engineering