Scripting, EMIR Signoff flow, Data Analysis, In-rush current profiles, EDA Tools, Dynamic vectored and vectorless Static IR, Power Distribution Network Design, On-die power gating, Problem Solving

Routing, Sta, CTS, PNR, Physical Design, floorplanning, Timing Closure, Placement, Sign-off

Perl, Python, Tcl, Timing Closure STA, RTL-to-GDSII Execution, Red Hawk, Programming Scripting, Fusion Compiler, LEC, Tempus, Cross-Functional Collaboration, Physical Formal Verification, Innovus, Calibre, primetime, PPA Optimization, EDA Tools, VCLP

Logic Design, Physical design architecture, P R Timing and Physical verification tools, floorplanning, Physical implementation flows, Physical design flows

Scripting, Static Timing Analysis, Routing, Design Compiler, CTS, primetime, ICC2, Synopsys Fusion Compiler, LVS, Cadence Genus, Innovus, Physical Verification, Formal Equivalence, Extraction, StarRC, Placement, RTL to GDS2 flow, Floor-plan Physical Implementation, Power-plan Synthesis, Apache Redhawk, Mentor Graphics Calibre, Crosstalk Analysis, EM, Ir, Physical Design, Timing Closure, DRC, PNR tools

Sta, PG creation and push-down methodologies, Physical Verification, SoC RTL to GDSII implementation, Scripting flow deployment, RDL knowledge, SoC Full-chip floorplanning, Die file generation, Feed-through planning, Hierarchical design implementation, PnR implementation

static timing analysis, Perl, Tcl, Makefile scripting, Synthesis, physical design CAD flow, Mentor Calibre, Power Distribution, Cadence Innovus, Cadence Genus, Floor Planning, physical design verification

Synthesis, physical verification closure, Formal, Timing Closure, block chip level implementation from Netlist to GDS, scripting skills – TCL

Scripting, EMIR Signoff flow, In-rush current profiles, Data Analysis, EDA Tools, Dynamic vectored and vectorless Static IR, Power Distribution Network Design, On-die power gating, Problem Solving

Shell, Perl, Python, Tcl, Ecos, Flows, automation, Innovus, primetime, ICC2, Tempus, FusionCompiler, Design Reviews, EM closure, Ir, PD methodologies, tapeout readiness, RTL-to-GDSII flow, Timing Closure, Si, PPA optimization