Register modeling, Regression management, SERDES, coverage analysis, Uvm, Firmware interaction, systemverilog, PHY architectures

Shell, Perl, Python, Tcl, Assertions SVA, UVM methodology, Debugging RTL verification issues, Coverage-driven verification, systemverilog, Functional Verification

Perl, Makefile, Ruby, Python, C-DPI, Axi, AMBA, ASIC verification tools, Uvm, AHB, systemverilog

Pcie, Perl, Python, AMBA, Axi, APB, AHB, System Verilog assertions, systemverilog

Jtag, Pcie, Perl, Python, System Verilog, Tessent Embedded Analytics, UltraSoC, RISC Debug Architecture, UVM methodology, Design for Debug, High speed USB

Usb, Fpga, Perl, Pcie, Python, verification methodologies, coverage driven verification, Emulation, directed constrained-random tests, Uvm, systemverilog, formal verification, MIPI, AMBA, Test Bench, transaction level modeling, AXI4

Usb, Fpga, Perl, Pcie, Python, verification methodologies, Emulation, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, AMBA, MIPI, formal verification, Test Bench, transaction level modeling, AXI4

Usb, Fpga, Pcie, Perl, Python, verification methodologies, Emulation, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, AMBA, formal verification, MIPI, Test Bench, transaction level modeling, AXI4

System Verilog, Building test benches from scratch, ASIC verification using UVM