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Showing 4 jobs
Skills:
Vcs, Perl, Python, Tcl, Scan Insertion, Post-silicon validation, BScan, P1687, TetraMax, Gate level simulation debugging, ATE patterns, JTAG protocols, ATPG, Tessent tool sets, TestMax
Skills:
System Verilog, Vcs, Logic Equivalency checking, Gate level simulation debugging, JTAG protocols, ATPG, Scan and BIST architectures
Skills:
Vcs, Tcl, System Verilog, Python, Perl, TetraMax, Logic Equivalency checking, TestMax, EDA Tools, JTAG protocols, ATPG, Scan and BIST architectures, Tessent, primetime
Skills:
System Verilog, Vcs, Gate level simulation debugging, Logic Equivalency checking, JTAG protocols, ATPG, Scan and BIST architectures
