Phase Interpolator, Cadence tool experience, CAD tools for circuit simulation, CMOS design, Bias and Bandgap Voltage Regulators, SERDES, jitter and signal equalization techniques, High Speed Clock Distribution, Low jitter PLL, layout and physical verification

Verilog, Usb, Pcie, RTL Coding, systemverilog, Datapath design, FIFO design, Microarchitecture, SERDES, MIPI D-PHY

closure , code coverage , Test Plan Creation, Verilog, Usb, UVM methodology, Mixed-mode simulations, Functional Verification, Emulation, SERDES, GLS debug skills, Automotive IP verification, Assertions development, SV, UCIe, Functional coverage, Analog models, Fault injection, Verification environment planning, Digital verification, Power-aware RTL set-up, Gate-level simulations, Simulation and debug, Constraint randomization, formal verification, HVL, DPHY

ISO 26262 Safety compliance for automotive memory IPs, Yield analysis, CMOS analog digital circuit design principles, Memory compiler design and automation, Memory Characterization, ECC redundancy and repair strategies, silicon debug

Synopsys, compensation techniques, high-speed TX, analog mixed signal design, Siemens, EDA Tools, noise analysis, transistor capacitor matching, transistor level circuit design, Pll, SERDES, Cadence