Verilog, Usb, Pcie, RTL Coding, systemverilog, Datapath design, FIFO design, Microarchitecture, SERDES, MIPI D-PHY

Cadence tool experience, jitter and signal equalization techniques, Phase Interpolator, layout and physical verification, CMOS design, High Speed Clock Distribution, Bias and Bandgap Voltage Regulators, Low jitter PLL, CAD tools for circuit simulation, SERDES

code coverage , closure , Usb, Test Plan Creation, Verilog, Assertions development, formal verification, Functional coverage, UCIe, Power-aware RTL set-up, SV, Gate-level simulations, Emulation, Fault injection, HVL, Constraint randomization, Automotive IP verification, Analog models, DPHY, UVM methodology, Mixed-mode simulations, Digital verification, Verification environment planning, Functional Verification, GLS debug skills, Simulation and debug, SERDES

Matlab, Device physics and process technologies, Simplis, IC system partitioning and architectural tradeoff analysis, Physical layout management, Analog Circuit Design, Spectre, Post layout parasitic extraction and simulation verification

telemetry , monte carlo , Python, Analog Mixed-Signal Design, Stability Compensation, Precision Circuits, Advanced CMOS Processes, Spectre, PVT Mismatch, Aging, Noise PSRR, Cadence Virtuoso, Variation Reliability

ISO 26262 Safety compliance for automotive memory IPs, Yield analysis, CMOS analog digital circuit design principles, Memory compiler design and automation, Memory Characterization, ECC redundancy and repair strategies, silicon debug

Synopsys, compensation techniques, high-speed TX, analog mixed signal design, Siemens, EDA Tools, noise analysis, transistor capacitor matching, transistor level circuit design, Pll, SERDES, Cadence