CAD tools for circuit simulation, CMOS design, SERDES, jitter and signal equalization techniques, layout and physical verification

Phase Interpolator, Cadence tool experience, CAD tools for circuit simulation, CMOS design, Bias and Bandgap Voltage Regulators, SERDES, jitter and signal equalization techniques, High Speed Clock Distribution, Low jitter PLL, layout and physical verification

Logic Design, DDR, AMS verification, system level design, Mixed Signal IP design, AMS design techniques, High-speed circuits, Lab debugs on AMS IPs, Tx Rx CTLE Amplifiers Samplers, Analog Mixed Signal design, HBM technologies, Circuit architecture, SERDES

static timing analysis, Python, Verilog RTL, Genus Design Compiler, scripting or programming languages, DFT methodologies, high-speed SerDes, ASIC synthesis, Asic Physical Design, physical verification DRC LVS, 3DIC implementation methodologies, Cadence Virtuoso, RTL Compiler, place-and-route Encounter Innovus ICC, Clock Tree Synthesis

high-speed AMS circuits, SerDes design, lab equipment for testing and characterization, high-speed digital design, circuit simulation and analysis, TX RX and PLL components, signal integrity analysis