Jtag, Perl, coverage improvement techniques, post-silicon bring up, block level and chip STA flows, scan insertion techniques, DFT IP integration, Memory BIST generation, MBIST, test mode timing constraints, Analog Macro tests, gate level simulation, chip tape out, Fault Models, debug on ATE, ATPG, timing SDF simulations, Scan, test point insertion, Cadence Tessent tools