Job Description: FPGA Design Engineer (3-5 Years Experience)

Role Overview

We are seeking an experienced FPGA Design Engineer with 3-5 years of hands-on expertise in FPGA development, design flow, and hardware debugging. The ideal candidate will have strong knowledge of FPGA tools, RTL design, and protocols, with exposure to domain-specific applications such as SDI, DisplayPort, HDMI, and Ethernet.

Key Responsibilities

Design, implement, and verify FPGA-based solutions across multiple domains.
Work with FPGA design flow including synthesis, place-and-route (PNR), and timing closure.
Perform timing analysis and resolve timing-related issues.
Conduct simulation using Questasim and validate designs.
Debug hardware in lab setups using oscilloscopes, analyzers, and FPGA debuggers.
Enhance and maintain design documentation based on project updates and improvements.
Collaborate with cross-functional teams to integrate FPGA designs into larger systems.

Required Skills & Experience

Strong knowledge of FPGAs and hands-on experience with Synthesis and Implementation tools, like Libero or Vivado or Quartus.
Proficiency in RTL design (Verilog/VHDL).
Experience with FPGA hardware platforms and lab-based validation.
Hands-on experience with Tcl scripting for automation.
Understanding of IPs such as Transceivers, DDR, and PCIe.
Familiarity with simulation tools like Questasim.
Strong debugging skills using hardware tools (oscilloscopes, analyzers, etc.).

Domain Knowledge (Preferred)

SDI, DisplayPort, HDMI 2.2, SLVS OR
Motor Control, Holoscan OR
TSN (Time-Sensitive Networking), Ethernet protocols

Desired Attributes

Strong problem-solving and analytical skills.
Ability to work independently and in collaborative team environments.
Excellent documentation and communication skills.
Passion for exploring new FPGA trends and applying them to real-world applications
FPGA Design and Validation experience
Experience validating FPGA designs on Board
Should be able to use Oscilloscopes
Usage of Spirent or other Traffic generator tools will be added advantage
Proficient with scripting language like TCL
Good understanding of Lint, CDC is desired
Knowledge of usage of AI Agents and Prompt Engineering is a plus.

SENIOR ENGINEER - FPGA design techniques