Simulation and Debug Tools (VCS, Verdi), System Verilog, Verilog, UVM Methodology, Functional Coverage and Assertions, C/C++ or Python Scripting

Analog Circuit Design, Design Verification, Monte Carlo analysis, Modern CAD tools, Silicon validation and debug, Analog layouts, Simulation and Verification, Transistor level design flow, Schematic generation

transceivers , regulators , Dll, MATLAB, ADC, Tx, Rx, analog IC design, Spectre, high-speed SerDes, Pll, Hspice, CDR, Cadence Virtuoso

Dac, ADC, IC layout design techniques, Frequency Synthesizers, Front-end RF and Analog circuit blocks, IC design tools and simulators, mixers, Continuous-Time Filters, Driver amplifiers, Verification methodologies, LNAs, Analog RF IC circuit design, TX modulators, RF Analog circuit design in sub-90nm CMOS

Perforce, static timing analysis, Shell, Verilog, Version Control Systems, Scripting Languages, Python, Git, Perl, Tcl, cdc, Simulation, formal verification, EDA Tools, Rtl Design, Synthesis, SoC Architecture Design, LEC, AMBA protocols, systemverilog, Axi, APB, LINT, AHB, SoC Integration

Understanding of low-power design flows, ATPG and test coverage analysis using industry standard tools, Gate level simulation using Synopsys VCS and Verdi, Knowledge of fault models, JTAG Scan Compression and ASST implementation, Fluent in RTL coding for DFx logic, Exposure to post-silicon testing and tester pattern debug, Familiarity with SystemVerilog and UVM, Understanding of DFT Architectures and micro-architectures, MBIST planning implementation and verification