Perl, Networking, hw design, Uvm

Register modeling, Regression management, SERDES, coverage analysis, Uvm, Firmware interaction, systemverilog, PHY architectures

Perl, Makefile, Ruby, Python, C-DPI, Axi, AMBA, ASIC verification tools, Uvm, AHB, systemverilog

Perl, Verilog, Python, Tcl, quartus, VHDL, Vivado, FPGA IP Design Validation, Vlsi Design, systemverilog