bandgap references , regulators , Data-path analog blocks, Interface Circuits, PLL clock-generation, Mixed-signal circuit design, Layout collaboration, Custom analog design, Charge Pumps, Analog Design, Transistor-level design, Parasitic-aware optimization, Loop Filters, Bias circuits, Simulation and optimization

Analog Circuit Design, Design Verification, Monte Carlo analysis, Modern CAD tools, Silicon validation and debug, Analog layouts, Simulation and Verification, Transistor level design flow, Schematic generation

regulators , Dll, MATLAB, Debugging, ADC, ADE, lab chip bring-up, analog layouts in FinFet, Spectre, Pll, system level pre-tape out analog validation, Signal Integrity, TX RX CDRs, Multi-GHz low-jitter clock generation, Amplifiers, Spice, virtuoso, noise reduction

C, Tcl, Python, Perl, PrimeSim, LVS, CMOS design, Spectre, ADE, high-speed analog design, Custom Compiler, post-layout extraction, Cadence Virtuoso, DRC, Hspice, Circuit Simulation

Caliber DRC, Virtuoso XL, ERC, cadence LVS, LVS verification and debugging tools, layout design and verification tools, rmap

matching , rc extraction , shielding , bandgap references , Perl, Tcl, ADC, latch-up strategies, Skill, high-speed analog custom layout, LVS, Power Planning, Dfm, Pll, clock routing, SERDES, Esd, EDA Tools, ERC, EMIR analysis, DRC, Cadence Virtuoso, LDOs