Vcs, Perl, Python, Tcl, Xcelium, AMBA-based interconnect fabrics, AXI-Lite, Uvm, systemverilog, Axi, APB, AI-assisted engineering tools, Questa, AHB

Machine Learning, Data Analytics, Python, Deep Learning, Document-processing pipelines, LLM-based workflows

boundary scan , ATPG (Automatic Test Pattern Generation), LBIST (Logic Built-In Self-Test), DFT DRC (Design Rule Checking), Jtag, Perl, Python, Tcl, LINT, ASIC design flow, cdc, Scan compression, Scan stitching, Low power DFT Techniques, RTL Coding, ATPG Coverage improvement, DFT STA Constraint development, Analog Phy DFT

Tcl, System Verilog, Python, Perl, Vcs, Questa, Uvm, Modelsim

PowerShell, Python, SOTI MobiControl, HP Thin Clients, Enterprise MDM

Static timing analysis, ASIC development flow, Constraints generation, SOC design, Sta, Timing Closure