Perl, Tcl, Constraints Generation, power analysis using PTPX, Synopsys Cadence Tools, Synthesis STA, Python scripting language, Equivalent Checks, Timing Closure, VHDL, Verilog Constructs, Timing Budgets, multi voltage designs using CPF UPF, Hierarchical Designs

cable BOMs, Siemens Nx, Teamcenter PLM, cable and cable-routing TPDs

Python, Tcl, Innovus, primetime, ICCompiler2, Fusion compiler, processor designs, EDA Tools, toplevel physical implementation, lower node technologies

Python, Tcl, ICCompiler2, primetime, Innovus, Fusion compiler, EDA Tools, processor designs, toplevel physical implementation, lower node technologies

static timing analysis, Synthesis, signal integrity analysis, pads log management, Place And Route, RDL routing, Floor Planning, EDA tools for physical design and verification, power grid design, full-chip physical design, Timing Closure, bump placement, Clock Tree Synthesis

Tcl, Python, processor designs, primetime, EDA Tools, Fusion Compiler, ICCompiler2, Innovus, lower node technologies, toplevel physical implementation

Tcl, Python, Fusion Compiler, processor designs, primetime, EDA Tools, ICCompiler2, Innovus, lower node technologies, toplevel physical implementation