Siemens Nx, Teamcenter PLM, cable and cable-routing TPDs

Mentor Graphic Calibre DRC, Analog Layout fundamentals, Cadence VLE, AI-related tools

Tcl, Python, lower node technologies, processor designs, Fusion compiler, primetime, EDA Tools, ICCompiler2, Innovus, toplevel physical implementation

static timing analysis, signal integrity analysis, full-chip physical design, pads log management, Floor Planning, RDL routing, Place And Route, bump placement, EDA Tools, Synthesis, power grid design, Timing Closure, Clock Tree Synthesis

Physical Design, UPF, Place Route, formal verification, Fusion Compiler, Floorplan, Innovus, Power-Plan, Cadence

primetime, Fusion Compiler, low-power methodologies, Cadence Innovus, Tempus, Timing Analysis, Synopsys ICC2, EDA tool automation, ECO flows