Shell, Perl, Makefile, Ruby, Innovus, Fusion compiler, primetime, EDA Tools, Lower node technologies, Toplevel Physical implementation, Processor designs

Tcl, Python, processor designs, Fusion compiler, primetime, EDA Tools, ICCompiler2, Innovus, lower node technologies, toplevel physical implementation

Tcl, Python, primetime, Innovus, ICCompiler2, Fusion compiler, EDA Tools, processor designs, toplevel physical implementation, lower node technologies

static timing analysis, signal integrity analysis, Synthesis, pads log management, Place And Route, RDL routing, Floor Planning, power grid design, EDA Tools, full-chip physical design, Timing Closure, bump placement, Clock Tree Synthesis

Python, Tcl, lower node technologies, primetime, Innovus, ICCompiler2, Fusion compiler, EDA Tools, processor designs, toplevel physical implementation

boundary scan , ATPG (Automatic Test Pattern Generation), LBIST (Logic Built-In Self-Test), DFT DRC (Design Rule Checking), Jtag, Perl, Python, Tcl, LINT, ASIC design flow, cdc, Scan compression, Scan stitching, Low power DFT Techniques, RTL Coding, ATPG Coverage improvement, DFT STA Constraint development, Analog Phy DFT

routing, Physical Design, Place And Route, PNR, floorplanning, CTS