Pcie, Perl, Python, AMBA, Axi, APB, AHB, System Verilog assertions, systemverilog

Register modeling, Regression management, SERDES, coverage analysis, Uvm, Firmware interaction, systemverilog, PHY architectures

Verilog, random stimulus, VMM, assertion-based verification, Uvm, systemverilog, functional coverage, advanced verification methodologies

Perl, Makefile, Ruby, Python, C-DPI, Axi, AMBA, ASIC verification tools, Uvm, AHB, systemverilog

Perl, Verilog, Python, Tcl, quartus, VHDL, Vivado, FPGA IP Design Validation, Vlsi Design, systemverilog

Vcs, Perl, Python, Tcl, Debugging methodologies, Verdi, Assertions SVA, Xcelium, Uvm, ASIC SoC Verification Flows, systemverilog, Coverage-driven verification, spyglass, Simulation and regression flows, Jenkins Regression Automation Tools, DVE, Questa, Functional Verification