C, Verilog, System Verilog, IP level ASIC verification, Writing and debugging testbenches, Debugging SOC IO interfaces with Transactor solutions, SOC design model build experience, Debugging firmware and RTL code using simulation tools, Hands-on experience on Zebu Palladium Veloce platform, CPU GPU and Memory subsystem, BIOS OS bring up on full X86 SOC emulation platform, Verification methodologies, Understanding of PCIe USB Ethernet standards

C, Verilog, System Verilog, IP level ASIC verification, Writing and debugging testbenches, Debugging SOC IO interfaces with Transactor solutions, SOC design model build experience, Debugging firmware and RTL code using simulation tools, Hands-on experience on Zebu Palladium Veloce platform, CPU GPU and Memory subsystem, BIOS OS bring up on full X86 SOC emulation platform, Verification methodologies, Understanding of PCIe USB Ethernet standards

C, Verilog, System Verilog, IP level ASIC verification, Writing and debugging testbenches, SOC design model build experience, Debugging firmware and RTL code using simulation tools, Hands-on experience on Zebu Palladium Veloce platform, CPU GPU and Memory subsystem, BIOS OS bring up on full X86 SOC emulation platform, Debugging SOC IO interfaces with Transactor solutions in Emulation platform, Understanding of PCIe USB Ethernet standards

C, Verilog, Gdb, System Verilog, Python, Tcl, Zebu, Veloce, Palladium, waveform debuggers

C, Vcs, Gdb, Spi, Pcie, Perl, Ethernet, I2c, Python, Tcl, ProtoCompiler, HAPS 80, ASIC Logic RTL Design, Palladium, FPGA prototyping, quartus, AMBA, Zebu, Vivado, Veloce, Modelsim, VPS

C, Verilog, System Verilog, IP level ASIC verification, Writing and debugging testbenches, SOC design model build experience, Debugging firmware and RTL code using simulation tools, Hands-on experience on Zebu Palladium Veloce platform, CPU GPU and Memory subsystem, BIOS OS bring up on full X86 SOC emulation platform, Debugging SOC IO interfaces with Transactor solutions in Emulation platform, Understanding of PCIe USB Ethernet standards

Test Execution, emulation tool flows, pre-silicon verification testbench environments, Simulation Tools, SoC emulation model development, debug methodologies

Usb, Spi, DDR, Shell, Pcie, Perl, Pci, Sata, I2c, Ruby, System Verilog, Python, Tcl, Palladium, Axi, Emulation FPGA, Zebu

Spi, C, Uart, Scripting, Verilog, System Verilog, I2c, Ethernet, Pcie, Trace32, Can, waveform debugging, High-Speed IPs, ARM based SOC architecture, DV Acceleration, UFS, Transactor API integration, Verdi, AVIPS, Transcators, Zebu Emulator, CSI, Emulation models, Palladium

C, Verilog, Gdb, Python, System Verilog, Tcl, Zebu, Veloce, Palladium, waveform debuggers