Perl Scripting, Sta, High Speed Cores, Circuit Level Comprehension, RTL to GDSII Implementation, Leakage Power, Signal Integrity, Multi-Vt Flow, IC design, Dfm, Power Supply Management, Deep Sub-Micron Design, Physical Design, Power Gating, High Frequency Design Convergence, PDN Methodology, PPA Targets, Timing Signoff

rc extraction , Dac, Perl, Tcl, ADC, Skill, high-speed analog custom layout, LVS, Dfm, Physical Verification, Pll, SERDES, EDA Tools, EMIR analysis, ERC, DRC, Cadence Virtuoso

Logic Design, Perl, Python, Tcl, Sta, MBIST OCC validation flows, Mentor, Cadence, Physical design flows, SpyGlass DFT rules, Scan insertion and ATPG tools, Hierarchical DFT and SDC constraint management, Digital Circuit Design, SSN design and IEEE 1687 IJTAG standards, Synopsys, RTL design synthesis

scoreboard , Perl, Scripting Languages, Python, Uvm, Agents, constrained random techniques, sequencers, HVLs, testbenches, Gate simulations, debugging RTL, monitors

Perl, Python, Tcl, primetime, RTL-to-GDS recipes, Physical Design, Fusion Compiler, Synopsys Fusion Design Platform, IC Compiler II, AI ML optimization tools, Synopsys DSO.ai