layout and physical verification, jitter and signal equalization techniques, Cadence tool experience, Phase Interpolator, CMOS design, High Speed Clock Distribution, Bias and Bandgap Voltage Regulators, Low jitter PLL, CAD tools for circuit simulation, SERDES

code coverage , closure , Usb, Test Plan Creation, Verilog, Assertions development, formal verification, Functional coverage, UCIe, Power-aware RTL set-up, SV, Gate-level simulations, Emulation, Fault injection, HVL, Constraint randomization, Automotive IP verification, Analog models, DPHY, UVM methodology, Mixed-mode simulations, Digital verification, Verification environment planning, Functional Verification, GLS debug skills, Simulation and debug, SERDES

Verilog, Tcl, Ethernet, Perl, C, Scripting Languages, Pcie, AHB, Flash interfaces, RDC constructs, IP Synthesis, IP development flow, QuadSPI, FPGA Emulation Board, Axi, SERDES, BUS Protocols, HDLs, DDR4, High Speed Serial protocols, ATPG, cdc, AMBA, Testplan development, VHDL, microcontroller architecture, pre silicon validation, LPDDR4, Dft

Usb, Ethernet, I2c, MIL-STD-461 Testing, Requirements Capture and Traceability, Signal Integrity Analysis, Troubleshooting using engineering laboratory equipment, schematic capture, Digital Electronics Design, DDR3 Memory Interfaces, Timing Analysis, SERDES Interfaces, LVDS, DO-160 Testing, MIL-STD-810 Testing

ISO 26262 Safety compliance for automotive memory IPs, Yield analysis, CMOS analog digital circuit design principles, Memory compiler design and automation, Memory Characterization, ECC redundancy and repair strategies, silicon debug

Synopsys, compensation techniques, high-speed TX, analog mixed signal design, Siemens, EDA Tools, noise analysis, transistor capacitor matching, transistor level circuit design, Pll, SERDES, Cadence