C, Python, Perl, MATLAB, Parasitic Extraction, High-speed SerDes circuits, systemverilog, Mixed-signal verification, Verilog-A, Cadence Virtuoso, RF ADE, Spectre

layout and physical verification, jitter and signal equalization techniques, Cadence tool experience, Phase Interpolator, CMOS design, High Speed Clock Distribution, Bias and Bandgap Voltage Regulators, Low jitter PLL, CAD tools for circuit simulation, SERDES

Verilog, Tcl, Ethernet, Perl, C, Scripting Languages, Pcie, AHB, Flash interfaces, RDC constructs, IP Synthesis, IP development flow, QuadSPI, FPGA Emulation Board, Axi, SERDES, BUS Protocols, HDLs, DDR4, High Speed Serial protocols, ATPG, cdc, AMBA, Testplan development, VHDL, microcontroller architecture, pre silicon validation, LPDDR4, Dft