layout and physical verification, jitter and signal equalization techniques, Phase Interpolator, CMOS design, High Speed Clock Distribution, Bias and Bandgap Voltage Regulators, Low jitter PLL, CAD tools for circuit simulation, SERDES

power management, Scripting and automation, IP integration, Custom layout design, Physical verifications, LVS, Analog layout techniques, Ageing and Reliability Compliance, Data converters, Floorplan constraints, Analog Macros, DRC, Electrical check, Full Spectrum Verifications, High-speed Analog Serdes, Pll, High-speed IPs