Verilog, Oops Concepts, scripting and tool development using Perl, VCS or equivalent simulation tools, debug tools like Debussy GDB, VMM, Uvm, systemverilog

Keysight, Exercisers, LeCroy, PIPE Interface verification, Uvm, PCIe Protocol Gen5, systemverilog, Protocol Analyzers

test tools automation, System Security Privacy Engineering UNECE WP29, Functional Safety Management ISO26262, C-driven, Uvm, systemverilog

Noc, C, Pcie, Perl, Python, Reset and power verification, SOC verification methodologies, SOC bring-up, Uvm, Post-silicon verification, Axi, HW FW interaction verification, Coherency verification, Bus Fabric, AHB, UPF integration

code coverage , Python, C, Debugging, Shell, Tcl, Verilog, System Verilog, Perl, Uvm, constrained random methodologies, Metric Driven Verification, assertions, functional coverage, formal verification methodologies

Test Planning, Ovm, Debugging, CHI, Uvm, system simulation tools, AHB, UVM-based test benches, SoC design verification, APB, Axi, emulation models, AMBA protocols

Shell, Perl, Python, formal property verification, complexity reduction techniques, formal verification technologies, formal testbenches, testplans

Shell, Python, Perl, Scripting Languages, DACs, Uvm, SV, Dms, behavioral modeling, Signal Processing, digital RTL, ADC, Synopsys VCS, Analog Mixed Signal, DV, full chip verification, Cadence Virtuoso, verification plan, Oscillators, Pll, Debug