Verilog, Python, bus architectures, Synopsys, performance modeling tools, Cadence Tools, accelerators, memory hierarchies, low-power design techniques, arithmetic units

Verilog, Logic Design, Physical Design, Timing Constraints, RTL constraints, LINT, Vlsi, timing exceptions, System-Verilog, cdc

2d graphics , Verilog, C++ Programming, Opengl, Directx, Gpu, RTL, 3D Graphics, systemverilog, Rtl Design

Uart, Spi, Verilog, I2c, LINT, cdc, MAS development, Sub-system design, SoC integration, ip design, Quality check flows, AMBA bus protocols, Axi, APB, RTL Coding, Medium complexity protocol, AHB, Microarchitecture