C, Makefile, Windows, Linux, Perl, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, UVM testbenches, simulation profile efficiency improvement, TLM, developing UVM based verification frameworks, debugging firmware and RTL code using simulation tools, acceleration HLS tools process, automating workflows in a distributed compute environment

C, Makefile, Windows, Perl, Linux, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, acceleration HLS tools process, UVM testbenches, automating workflows in a distributed compute environment, developing UVM based verification frameworks, simulation profile efficiency improvement, TLM, debugging firmware and RTL code using simulation tools

C, Makefile, Windows, Perl, Linux, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, UVM testbenches, simulation profile efficiency improvement, UVM based verification frameworks, TLM, debugging firmware and RTL code using simulation tools

Makefile, Windows, Linux, Pcie, Perl, Verilog, System Verilog, IP level ASIC verification, LLMs, HLS tools, AI Agents, UVM testbenches, DMA verification, Simulation profile efficiency improvement, UVM based verification frameworks, CXL

Perl, Python, SV – UVM Assertions based verification, RTL debug skills, ARM based system architecture, industry-standard simulation tools, power aware simulation, RTL design verification, Uvm, systemverilog, Firmware emulation, camera verification, Coverage closure, dpi

Computer Architecture, Perl, Debugging, Python, Formal Verification methodologies, IP SOC verification, Functional Verification, Uvm, systemverilog, Rtl Design