Windows, Linux, Pcie, Verilog, System Verilog, IP level ASIC verification, HLS tools, UVM testbenches, DMA verification, automating workflows, UVM concepts, simulation profile efficiency improvement, UVM based verification frameworks, CXL, testbenches processes and flows, LLMs AI Agents in verification

C, Makefile, Windows, Linux, Perl, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, acceleration HLS tools process, UVM testbenches, automating workflows in a distributed compute environment, developing UVM based verification frameworks, simulation profile efficiency improvement, TLM, debugging firmware and RTL code using simulation tools

C, Makefile, Windows, Perl, Linux, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, acceleration HLS tools process, UVM testbenches, automating workflows in a distributed compute environment, developing UVM based verification frameworks, simulation profile efficiency improvement, TLM, debugging firmware and RTL code using simulation tools

Windows, Pcie, Linux, Verilog, System Verilog, automation, HLS tools, DMA verification, CXL, simulation profile efficiency improvement, Ai, Uvm

C, Makefile, Windows, Linux, Perl, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, acceleration HLS tools process, UVM testbenches, automating workflows in a distributed compute environment, developing UVM based verification frameworks, simulation profile efficiency improvement, debugging firmware and RTL code using simulation tools, TLM