Structural Design, Wind turbine component design criteria, Project management, Technical drawing guidelines, FE analysis

static timing analysis, Verilog, Python, Tcl, SDC development, Tempus, Cadence Innovus, simulation methodologies, Rtl Design, transistor-level concepts, Genus, digital circuit operation, custom layout fundamentals, place-and-route, multi-clock designs, Synthesis, digital design fundamentals, floorplanning, Physical Verification, systemverilog, CDC concepts, Timing Constraints, Liberty timing models, characterization concepts

SAP, vpm, AIRINA, 2D detailed drawings, Pdm, DPDS, Catia V5

bandgap references , power FETs, Schmitt Trigger, Monte Carlo analysis, Pspice, mismatch noise gain offset, Statistics, Amplifiers, ESD protection circuits, Level Shifter, transistor layout fabrication process, Analog Circuit Design, transistor level architectures, LDMOS, Comparators, Current Mirrors, Statistical Distributions, MOS Diodes

Pro Engineer, QFD, 3D CAD software, tolerance stack-up, PDM software, Dfmea, mechanism design, Six Sigma

Verilog RTL coding, spyglass, Verplex LEC, high-speed serial interfaces, Synopsys Design Compiler, multi-domain clock synchronization, high performance memory subsystems, ASIC debugging

React, Typescript, Javascript, CSS, HTML, Building Reusable Libraries, Design System Component Library

Computer Architecture, Perl, Debugging, Python, Formal Verification methodologies, IP SOC verification, Functional Verification, Uvm, systemverilog, Rtl Design