Shell, Perl, Verilog, Python, Tcl, UVM methodology, Cadence, systemverilog, Functional and code coverage, Simulation and debugging concepts, Verification tools from Synopsys, Siemens EDA

System Verilog, Building test benches from scratch, ASIC verification using UVM

Usb, Fpga, Perl, Pcie, Python, verification methodologies, coverage driven verification, Emulation, directed constrained-random tests, Uvm, systemverilog, formal verification, MIPI, AMBA, Test Bench, transaction level modeling, AXI4

Test Plan Creation, Verilog, Execution, DV environments, cdc, APB bus protocols, block functional models, BFM, Uvm, UPF, systemverilog, formal verification methodologies, VHDL, RDC, constrained random verification techniques, CPF, AHB

test environments , Test Cases, System Verilog, Test Planning, low-power design verification, verification test benches

DDR, Usb, C, Pcie, Uart, I2c, Spi, Object-Oriented Programming, I3C, Uvm, systemverilog

Pcie, Vcs, System Verilog, Security IPs, Verdi, Ethernet interfaces, Axi, FPGA simulation tools, performance grading, MACSec, UVM flow development

python, perl, System Verilog, Computer Architecture, Network on Chip verification, Configurable IP verification, coherency architecture, AMBA protocols, VIP integration, coherent protocols, bridge checkers, protocol checkers