Vcs, programming, Scripting, Python, System Verilog, Asic verification, NCSim, verification of HBM memory interfaces, UVM testbench development, verification of SerDes IP block interfaces, Modelsim, formal model equivalence checking

Autocad, Catia V5, Wiring harness design, regular expressions, ATIM, VeSyS2.0 wiring harness design tool, Wiring harness testing and inspection, Basic Python scripting, IPC-620 standard, CAD Tools, MENTOR TOOLS

security automation , Servicenow, Json, Iam, Siem, Rest Apis, Python, Email Security, Migrations, Vulnerability Management, Upgrades, Threat Intelligence, Palo Alto XSOAR, XDR, CrowdStrike, EDR, Splunk SOAR, Microsoft Security Technologies, SOAR Architecture, Platform Administration, Enterprise Deployments, SOAR Playbooks, Webhooks

System Verilog, DV methodologies and tools, Digital design concepts, LPDDR5 protocols, Debug, Uvm

Prometheus, Grafana, Datadog, Terraform, Splunk, Helm, Kubernetes, Python, AWS, GitOps, Go, ArgoCD

System Verilog, Building test benches from scratch, ASIC verification using UVM