About TylSemi, Inc.

The Opportunity

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package

That's what we solve. TylSemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

This isn't a nice-to-have. It's the critical path.

Why Now

The Market Window

The semiconductor industry is going through its biggest architectural shift in 40 years:

Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.
Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.
IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.

Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.

Culture & Team: How We Work

No Politics, No Bureaucracy

There are no layers, no approval chains, no corporate theater.

If you have an idea, we test it. If it works, we ship it.
No endless meetings, no PowerPoint presentations to convince middle management.

Remote-Friendly, Global Team

US team: Bay Area preferred, but we hire the best people regardless of location
India team: Building a world-class design center in Bangalore

Move Fast, Ship Real Products

We're not a research project. We have paying customers, committed capital, and aggressive timelines.

This is a company, not a lifestyle business. We're building to win.

What We Value

Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it.
Bias for action. We move fast. Analysis paralysis doesn't fly here.
Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.
Low ego, high standards. We don't care about titles or politics. We care about results.

The Ask

If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.

We're asking you to walk away from that and bet on us.

Here's Why You Should

The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.
The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.
The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.
The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.

This is the bet. Join us and build something that matters.

Or stay comfortable. No judgment.

But if you're the kind of person who wants to take the shot, we'd love to talk.

READY TO JOIN

We are looking for a PCIe Sub-system Front-end RTL lead for next generation chiplet based SoCs for High-performance Compute and AI silicon .

Responsibilities

Own the PCIe subsystem microarchitecture from the PHY interface through the MAC and Transaction Layer, defining the internal block boundaries, data paths, and control interfaces.
Lead the integration of third-party PCIe controller and PHY hard IP, including wrapper RTL that adds mode selection, telemetry hooks, and bridging logic to the chiplet's internal fabric.
Define and implement the bifurcation and lane-configuration logic, ensuring all supported lane-width configurations operate correctly across the full range of operating modes.
Specify and drive implementation of the Transaction Layer pipeline: TLP reception, integrity checking, header classification, routing decisions, and handoff to downstream subsystems.
Own the Virtual Channel and flow-control architecture, ensuring fair arbitration and back-pressure handling across all traffic classes.
Define the integration interface to the PCIe subsystem such asTLP-to-flit adaptation, flow-control mapping, and error handling at the boundary.
Collaborate with the management firmware team to define the PCIe register map, mode-select interface, and run-time telemetry structures exposed to the on-chip management processor.
Work with the Physical Design Lead to meet timing closure requirements for the PCIe subsystem, including MAC-PHY interface timing, reset sequencing, and floorplan constraints.
Hold the PCIe performance budget for each operating mode: bandwidth efficiency, latency through the Transaction Layer, and error recovery overhead.
Define the PCIe power management architecture — link state transitions, ASPM policy, and integration with the chiplet-level power coordination scheme.
Lead PCIe silicon bring-up planning: define bringup sequence, debug instrumentation requirements, loopback modes, and the hand-off criteria for production readiness.
Mentor and guide RTL design engineers responsible for PCIe subsystem implementation, providing architectural guidance and RTL review.
Partner with the DV team to define the PCIe UVM verification plan, coverage model, and protocol-checker requirements.
Serve as the technical point of contact for PCIe-related customer integration questions, supporting anchor customer engagements on interface bring-up and interoperability.
Author and maintain the PCIe subsystem micro-architecture specification, keeping it current through RTL implementation and sign-off.

Required Qualifications

10+ years of digital IC design experience, with at least 4 years focused on PCIe subsystem design or integration at the block-lead or module-owner level.
Deep expertise in PCIe architecture: Transaction Layer, Data Link Layer, Physical Layer, TLP structure, flow control, Virtual Channels, and error handling.
Hands-on experience integrating PCIe hard IP (controller and/or SerDes PHY) into production SoC or chiplet designs, including wrapper RTL, reset sequencing, and PnR constraints.
Background in SR-IOV, multi-function device configuration, or host software driver interaction at the hardware level.
Strong SystemVerilog RTL skills: able to write, review, and own production RTL for complex pipelined state machines, FIFOs, arbiters, and control logic.
CXL 1.1/2.0 or 3.0 protocol knowledge, particularly CXL.io and CXL.mem transaction handling built on the PCIe fabric.
Solid understanding of PCIe PHY-MAC interface protocols and timing requirements,
Experience with PCIe compliance testing and PCI-SIG certification process — understanding of test requirements, common failure modes, and debug methodology.
Familiarity with PCIe power management, L0s/L1 state machines, state transitions etc.
Competency in multi-clock-domain design: async FIFO, CDC synchronizers, and clock crossing at the PCIe-to-internal-fabric boundary.
BS/MS in Electrical Engineering, Computer Engineering, or equivalent.

Preferred Qualifications

Experience with UCIe or another die-to-die protocol at the PCIe TLP adaptation layer — mapping TLPs to a flit-based D2D transport.
Prior experience with protocol bridging or gearbox designs that span multiple PCIe generations.
Familiarity with PCIe IP integration, including customization and support engagement.
Experience at an advanced-node (7 nm or below) tape-out, particularly with the timing closure and floorplan considerations for designs.

PCIe Subsystem RTL lead