C, Shell, Verilog, Python, Tcl, Systemc, Test Planning, systemverilog, constrained-random verification, formal verification, power-aware verification, UVM-based testbench development, NoC bus and interconnect verification

Shell, Pcie, Perl, Arm, Python, Tcl, MCU, AMBA, Axi, UCIe, systemverilog

static timing analysis, LINT, Logic Synthesis, Dft, cdc, formal verification, Cadence-based ASIC design environments, low-power design methodologies, micro-architecture development, SystemVerilog RTL design

Verilog, Computer Architecture, Subsystem hardening, Synthesis, object-oriented programming, floorplanning, Place And Route, DFT insertion, digital logic, VHDL, RTL-to-GDSII implementation, EDA Tools, Timing Closure, Clock Tree Synthesis

S3, PostgreSQL, Tibco, Lambda, Terraform, Docker, Sns, Python, Api Gateway, RDS, Cloudformation, Dynamodb, Shell Scripting, Jenkins, Cloudwatch, ECS, Sqs, Mulesoft, Dynatrace, Splunk, Kubernetes, AWS CDK, Secrets Manager, AWS X-Ray, Serverless Framework, EventBridge, AWS-native services, Step Functions, Glue

Perl, Verilog, Shell scripting, Python, Tcl, systemverilog, SVA