Job Location: Barcelona, Spain

Work Authorization: Visa sponsorship if required is provided

Job Title: Senior Design Engineer SoC & Coherency Verification Engineer (RTL + CHI + Embedded C)

About the Role

We are looking for a highly skilled SoC Design & Verification Engineer with strong expertise in RTL development, AMBA CHI protocol, coherency architecture, and embedded C/firmware integration. This is a hybrid role spanning front-end RTL design, interconnect coherency validation, and system-level bring-up.

You will contribute to next-generation SoC platforms, working across microarchitecture, RTL implementation, protocol verification, and hardware-software co-design.

Key Responsibilities

1. RTL Design & Microarchitecture

Design and implement high-quality RTL (Verilog/SystemVerilog) for SoC components
Develop microarchitecture specifications for interconnects, memory subsystems, and cache controllers
Work on high-performance, low-power designs with timing and area optimization
Integrate IPs into complex SoC subsystems

2. CHI / Coherency Design & Verification

Design and verify AMBA CHI (Coherent Hub Interface) based interconnects
Develop deep understanding of:
Cache coherency protocols (MESI/MOESI)
Snoop, data transfer, and ordering rules
Build test plans and verification strategies for coherency validation
Debug complex cache coherency issues at RTL and system level
Ensure protocol compliance and performance tuning

3. SoC Integration

Integrate multiple IP blocks (CPU, GPU, memory controllers, interconnects)
Work on SoC-level architecture and subsystem design
Handle clock/reset, power domains, and interconnect fabrics
Collaborate with physical design teams for timing closure and synthesis

4. Coherency Verification Engineering

Develop UVM-based verification environments
Write SystemVerilog testbenches, assertions, and checkers
Perform:
Functional verification
Coverage-driven verification
Regression and debug
Analyze waveform/debug tools for root-cause analysis

5. Embedded C / Firmware Integration

Develop embedded C firmware for:
Hardware bring-up
Feature validation
Debugging SoC behavior
Work on bare-metal / low-level drivers
Enable hardware-software co-validation
Debug system issues using firmware + RTL insights

6. PCB / PCS Exposure (Nice-to-Have / System Level)

Basic understanding of PCB design constraints and signal integrity
Familiarity with Physical Coding Sublayer (PCS) concepts (e.g., SERDES, Ethernet PHY interface)
Collaborate with hardware teams for board-level bring-up and validation

Required Skills & Qualifications

Core Technical Skills

Strong RTL design experience in:
Verilog / SystemVerilog
Deep knowledge of:
AMBA protocols (AXI / ACE / CHI)
Cache coherency protocols (MESI/MOESI)
Experience in SoC design and integration

Verification Skills

Expertise in:
UVM methodology
Functional and assertion-based verification
Experience with:
Coverage analysis
Debugging complex RTL issues

Embedded / Firmware

Strong programming skills in Embedded C
Experience with:
Low-level drivers
Hardware bring-up
Register-level programming

Tools & Technologies

Simulation: VCS, Xcelium, Questa
Debug: Verdi, DVE
Scripting: Python / Shell / Perl
Version control: Git

Good to Have

Experience with ARM-based SoCs
Exposure to NoC (Network-on-Chip) architectures
Knowledge of high-speed interfaces (PCIe, Ethernet, SERDES)
Understanding of DFT concepts
Exposure to FPGA prototyping/emulation

Experience

5–15 years of experience in SoC design / verification

Education

B.Tech / M.Tech in Electronics, Electrical, Computer Engineering, or related field

Key Competencies

Strong debugging and analytical skills
Ability to work across design + verification + firmware layers
Excellent collaboration with cross-functional teams
Ownership mindset for complex silicon programs

Renumeration range:

€50,000–€1,00,000 (Yearly)

€30–€50 (Hourly)

What do we offer Flexible work schedules, competitive pay, a highly learning environment, and opportunities for advancement.

Senior Design Engineer SoC & Coherency Verification Engineer in RTL, CHI & Embedded C