Dac, Perl, Tcl, GAA nodes, ADC, Skill, FinFET, deep sub-micron CMOS, LVS, Dfm, Pll, SERDES, ERC, EMIR analysis, EDA Tools, DRC, Cadence Virtuoso

shielding , Custom layout design, Clock routing, Layout automation, Cadence Virtuoso Layout XL GXL, Signal flow optimization, Reliability Analysis, SKILL scripting, Parasitic minimization, Device matching, Symmetry

Debugging Tools, Cadence LVS, RMAP, Verification Tools, Caliber DRC, ERC, LVS verification, Virtuoso XL