Dac, Tcl, Perl, Dfm, LVS, deep sub-micron CMOS, EDA Tools, ADC, ERC, Cadence Virtuoso, DRC, Skill, GAA nodes, FinFET, SERDES, Pll, EMIR analysis

Dac, Conducting reviews, ADC, Leading layout activities, Antenna and EMIR verification signoff methodologies, High-Speed Analog layouts, LVS, Custom IP Development, Pll, PHY Power Management, Analog Mixed-Signal Layout Design, ERC, DRC, LDO, Mentoring engineers

Vdc, ADC, Charge pump, density, Antenna, noise fixes, Vlsi Design, custom analog layout design, Virtuoso XL, EDA Tools, RV high voltage flows, LDO, scripting skills, layout validation, Circuit Design, DRCs

synopsys tools , Analog Circuit Design, Mentor Siemens Calibre, Physical Verification, ERC, DRC, Custom Layout, LVS, Cadence Virtuoso, Analog Layout Design