routing, Perl, Python, Tcl, ASIC design flow, Synthesis, Timing Analysis, signoff, EDA Tools, Timing Closure, Placement, PPA optimization, AI-driven productivity tools, RTL-to-GDSII

Tcl, Python, Perl, routing, signoff, ASIC design flow, PPA optimization, Timing Analysis, EDA Tools, Placement, Synthesis, Timing Closure, RTL-to-GDSII