boundary scan , Vcs, Perl, Python, Tcl, sdf debugging, Scan Insertion, Jtag protocols, memory BIST, TetraMax, Verilog design, p1687, p1500, ATPG, Gate level simulation, EDA Tools, Timing Closure, BIST architectures, Test static timing analysis, Tessent tool sets, timing based simulations, TestMax

boundary scan , Vcs, Python, Perl, Tcl, Scan Insertion, sdf debugging, DFT CAD development, Jtag protocols, DFT logic IP integration, p1687, p1500, EDA Tools, BIST architectures, Test static timing analysis, Tessent tool sets, Test Architecture Methodology, Infrastructure, memory BIST, TetraMax, Verilog design, Functional Verification, ATPG, Gate level simulation, Timing Closure, timing based simulations, TestMax

Static Timing Analysis, System Verilog, DFT CAD development, JTAG protocols, Logic Equivalency checking, ATPG, Post-silicon validation, Test Architecture Methodology, Scan and BIST architectures, Verilog design