test environments , Test Cases, System Verilog, Test Planning, low-power design verification, verification test benches

C, System Verilog, Scripting, digital design fundamentals, post Silicon validation, computer organization architectures, AMs, Uvm, BUS Protocols, Simulation, Low Power Verification, formal verification

Usb, Fpga, Perl, Pcie, Python, verification methodologies, coverage driven verification, Emulation, directed constrained-random tests, Uvm, systemverilog, formal verification, MIPI, AMBA, Test Bench, transaction level modeling, AXI4

System Verilog, Building test benches from scratch, ASIC verification using UVM

code coverage , perl, C, Regression Testing, Ovm, Pcie, Ethernet, Python, Uvm, systemverilog, Axi, DDR protocols, RTL simulators, X-propagation, functional coverage

DDR, Usb, C, Pcie, Uart, I2c, Spi, Object-Oriented Programming, I3C, Uvm, systemverilog

Unix, Unix Shell Scripts, Perl, Python, make, Uvm, systemverilog

System Verilog, Data path verification performance tests, Building test benches from scratch, Gate level simulation, ASIC verification using UVM