Debugging, Python, Tcl, Hardware-Software Co-Verification, Protocol Compliance Verification, formal verification, SoC Verification Expertise, Uvm, Processor-Based Verification, systemverilog, dpi

System Verilog, Assertion-based verification, Verification methodologies, Power-aware verification, Verification management tools, silicon debug, Gate-level simulation, Uvm, formal verification

Tcl Scripting, Pcie, Soc Architecture, Python, Axi, formal verification, regression management, BUS Protocols, simulation coverage analysis, Uvm, systemverilog

C, coverage closure, microprocessor ISA, coverage planning, Data-Consistency verification, power management verification, testbench development, clocking reset power-up sequences, low power verification flows, systemverilog

System Verilog, TLBs, Store buffer, Memory consistency models, Speculative loads, Physical register files, Flush replay, Debug tools, MMU, Cache hierarchy, Instruction fetch, Page table walkers, Interrupt handling, Register mapping, Protection, Uvm, LR SC, Reorder buffer, Bypass networks, Scheduler, Stores, Atomics, Coherence protocols, Decode rename, Issue queue