code coverage , C, Shell, Verilog, Debugging, Flash, Python, System Verilog, Perl, Tcl, interconnect, Memory, UVM methodology, Microprocessor architecture, clocking system modes, power management, SoC Verification, constrained random methodologies, Metric Driven Verification, Rom, formal verification methodologies, Axi, MRAM, AHB, Ram

C, Perl, Python, System Verilog, formal verification tools, Microarchitecture, SOC integration, Uvm

C, coverage closure, low power design verification techniques, coverage planning, Data-Consistency verification, power management verification, testbench development, clocking reset power-up sequences, x86 ISA, systemverilog

C, coverage closure, low power design verification techniques, coverage planning, Data-Consistency verification, power management verification, testbench development, x86 ISA, clocking reset power-up sequences, systemverilog

arm architecture , AI ML SoC exposure, Gate-Level Simulation, Cadence Tools, Arm Corestone, ATE pattern generation support, Test Bench Development, SystemVerilog UVM, ASIC SOC verification, Low-power verification experience, Functional Verification, AXI AHB APB Protocols

C, coverage closure, low power design verification techniques, coverage planning, Data-Consistency verification, power management verification, testbench development, x86 ISA, clocking reset power-up sequences, systemverilog

C, coverage closure, low power design verification techniques, coverage planning, Data-Consistency verification, power management verification, testbench development, clocking reset power-up sequences, x86 ISA, systemverilog

Coverage models, CPU Core Verification, Constrained-random tests, Scoreboards, Checkers, Architecture Validation, Uvm, systemverilog, Testbenches

arm architecture , C, Ethernet, Pcie, Usb, DDR, HBM, Uvm, SoC DV execution, assertion-based formal verification tools, TLMs in SystemC, hardware emulation support