Usb, C, Makefile, Windows, Shell, Pcie, Linux, Perl, Verilog, Ethernet, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, acceleration HLS tools, UVM testbenches, automating workflows in a distributed compute environment, AXI ACE Protocols, simulation profile efficiency improvement, UVM based verification frameworks, TLM, debugging firmware and RTL code using simulation tools

Test Bench development in System Verilog, Verification methodologies such as UVM, NAND Flash memory design, Understanding of StarRC Calibre parasitic extraction flow

arm architecture , AI ML SoC exposure, Gate-Level Simulation, Cadence Tools, Arm Corestone, ATE pattern generation support, Test Bench Development, SystemVerilog UVM, ASIC SOC verification, Low-power verification experience, Functional Verification, AXI AHB APB Protocols

System Verilog, dv methodologies and tools, DDR LPDDR families, Digital design concepts, Debug, Uvm

C, Systemc, Windows, Usb, Linux, Makefile, Shell, Verilog, Ruby, System Verilog, Ethernet, Pcie, Perl, automating workflows in a distributed compute environment, graphics pipeline knowledge, debugging firmware and RTL code using simulation tools, IP level ASIC verification, AXI ACE Protocols, UVM testbenches, HLS tools, TLM, UVM based verification frameworks, simulation profile efficiency improvement

C, System Verilog, IP verification, Uvm

Jtag, Pcie, Perl, System Verilog, Python, Tessent Embedded Analytics, UltraSoC, UVM methodology, Design for Debug, High speed USB, RISC Debug Architectures