Low Power SoCs, Physical Verification, Physical Design, Timing Closure, Floor Planning, Dynamic IR Drop, Package Co-design, Place And Route, Clock Tree Synthesis, IO Planning, Power Grid Design

Rtl Design, Synthesis, RISC CPU IP, Emulation, silicon bring-up, Microarchitecture, Verification, Timing Analysis, Physical Design, SoC design methodology

Perl, Python, Tcl, Timing Closure STA, RTL-to-GDSII Execution, Red Hawk, Programming Scripting, Fusion Compiler, LEC, Tempus, Cross-Functional Collaboration, Physical Formal Verification, Innovus, Calibre, primetime, PPA Optimization, EDA Tools, VCLP

Synthesis, Scripting automation, EDA Tools, Mixed signal complex IPs, AI and AI-enabled workflows, Critical paths of multi-GHz builds

bist , Verilog, C, Vcs, Python, AHB, microcontroller platforms, Timing Analysis, systemverilog, digital timing constraints, DFT methodologies, Cadence Virtuoso, APB, Axi, ASIC tool flows, Questa, Timing Constraints, high-speed SerDes, ATPG, FPGAs, AMBA, XCelium, SOC interconnect fabrics, Genus Design Compiler, Asic verification, Scan Insertion, ASIC synthesis

PERL, Python, Tcl, Synthesis, Formal Equivalence, DRC, Ir, LVS, EM Signoff