Perl, Python, Tcl, Clock domain partitioning, Power integrity and power-aware physical implementation, Block and subsystem-level physical design flows, primetime, Fusion Compiler, Clock gating, Congestion analysis and resolution, Clock tree architecture, Tempus, Cadence Innovus, Skew management, Certus, Synopsys ICC2, Timing closure and constraint management

Perl, Python, Tcl, Sta, Physical Design, ASIC Implementation, EM, Ir, PDN, make

Verilog, Microprocessors, Usb, Logic Design, Pcie, LINT, cdc, pad ring, SoC clocking, Design Compiler, Asynchronous interface, Synthesis, SDCC, RTL Coding, micro-architecture, Low power SoC design, System-Verilog, constraint development, SOC design, chip level floorplan, Memory controller designs, reset debug architecture, AMBA protocols, primetime, Axi, APB, timing concepts for ASIC, Timing Closure, Multi Clock designs, AHB

Unix, Lsf, Jenkins, Git, Shell, Linux, Verilog, Gitlab, Python, Tcl, Synthesis, cdc, Simulation, RTL, make, systemverilog, RDC, UGE, LINT, Low Power, Slurm

lattice , System Verilog, Usb, Verilog, Ethernet, Ddr3, C, Pcie, ARM Cortex platforms, SystemC-DPI testing methodologies, embedded processors, processor architectures, FPGA architectures, SERDES, AHB, Xilinx, VirtuaLAB environments, Altera, APB, RTL synthesis concepts, DSP theory, Veloce platforms, UVM-acceleration, AMBA, Microsemi

Ecos, Perl, Python, Tcl, FC PrimeTime, Sta, Design Compiler, CTS, EM, physical signoff, Ir, advanced-node SoCs, congestion optimization, ASIC Physical Design Full-Chip Implementation, MCMM, design closure, low-power implementation, PPA trade-offs, Synopsys ICC2