static timing analysis, Synthesis, RISC CPU IP, ARM CPUs, Emulation, chip validation, Timing Analysis, CPU microarchitecture, SoC design methodology, Physical Design, IP integration, CDC analysis, Rtl Design, Floor Planning, linting, BUS Protocols, Timing Closure, characterisation, silicon bring-up, Verification, equivalence checking

Java, Networking, Cloud Security, Sql, Nosql, Cloud Computing, Gcp, Apache Kafka, Python, Kubernetes, AWS, Ai, GCP Pub Sub

Perl, Python, Tcl, Logic Synthesis, Physical-Aware Synthesis, PPA optimization, UPF management, Low-Power Implementation, systemverilog

bist , Verilog, C, Vcs, Python, AHB, microcontroller platforms, Timing Analysis, systemverilog, digital timing constraints, DFT methodologies, Cadence Virtuoso, APB, Axi, ASIC tool flows, Questa, Timing Constraints, high-speed SerDes, ATPG, FPGAs, AMBA, XCelium, SOC interconnect fabrics, Genus Design Compiler, Asic verification, Scan Insertion, ASIC synthesis

Jenkins, Freebsd, Gcp, Linux, Shell scripting, C Programming, Azure, Python, AWS

automation, Python, Tcl, place-and-route, Cadence Innovus, Timing Analysis, Physical Verification

Schematic design, MATLAB, Python, Synopsys Custom Compiler, BERTs, Spectre, Hspice, Cadence Virtuoso, Layout interaction, behavioral modeling, Lab measurements, BER estimation, High-speed oscilloscopes, Post-layout verification, Design sign-off, Jitter budgeting, Parasitic Extraction, Silicon bring-up

Github, virtualization, OpenStack, Dns, Firewalls, routing, DHCP, Gcp, Terraform, shell scripting, Ansible, Pure Storage, Azure, Python, Kubernetes, AWS, networking fundamentals, Linux systems administration, Dell PowerStore, Infrastructure-as-Code