Perl, Python, Tcl, Clock domain partitioning, Block and subsystem-level physical design flows, primetime, Power integrity and power-aware physical implementation, Clock gating, Fusion Compiler, Congestion analysis and resolution, Clock tree architecture, Tempus, Cadence Innovus, Skew management, Certus, Synopsys ICC2, Timing closure and constraint management

Golang, Google Cloud Platform, Python, Sql, GenAI models, Google BigQuery

Pcie, Perl, Python, System Verilog, Tcl, CHI, SMMU, assertion-based verification, Uvm, Coresight, Axi, coverage-driven testing, CXL, SVA

bist , Verilog, C, Vcs, Python, ASIC tool flows, microcontroller platforms, Timing Analysis, systemverilog, digital timing constraints, DFT methodologies, AHB, Cadence Virtuoso, APB, Axi, Timing Constraints, high-speed SerDes, ATPG, FPGAs, AMBA, XCelium, Questa tools, SOC interconnect fabrics, Genus Design Compiler, Asic verification, ASIC synthesis, Scan Insertion

UPF, script writing in Python, UVM Test Bench development, power simulation on VCS

Orchestration, C++, Data Structures, Data Security, Sql, Python

Tensorflow, Machine Learning, Pytorch, Linux, Python, Pytest, Deep Learning, Transformers

Java, Oauth, Apis, Automated Testing, Sso, React, Typescript, Distributed Systems, Python, intelligent automation platforms, event-driven systems, platform engineering, LLM-powered applications, AI agents, authentication and authorization, cloud-native architectures, observability