Microsoft Hyper-v, BGP, C, Vmware Esxi, Gdb, Kvm, Wireshark, OSPF, Python, Qos, OpenStack, Go, qemu

Shell, Pcie, Perl, Arm, Python, Tcl, MCU, AMBA, Axi, UCIe, systemverilog

power optimization , Static Timing Analysis, Rtl Design, Physical Verification, DRC/LVS Checks, floorplanning, Place And Route, Signal Integrity, Timing Closure, Layout Optimization

Github, Sql, Shell scripting, Grafana, Ldap, Lsf, Tcl, Python, Perl, Jenkins, Gnu Make, Git, EDA Tools, Mentor Calibre, Synopsys VCS, Sungrid UGE, Cadence Virtuoso

Ml, Automation, Python, TCAD, Ai, device physics, Process Simulation

Verilog, Microprocessors, Usb, Logic Design, Pcie, LINT, cdc, pad ring, SoC clocking, Design Compiler, Synthesis, Asynchronous interface, SDCC, RTL Coding, Low power SoC design, micro-architecture, System-Verilog, SOC design, constraint development, chip level floorplan, Memory controller designs, reset debug architecture, AMBA protocols, primetime, Axi, APB, timing concepts for ASIC, Timing Closure, Multi Clock designs, AHB

Sql, Shell scripting, Grafana, Linux, Lsf, Tcl, Python, Perl, Jenkins, Git, Synopsys VCS, EDA Tools, Mentor Calibre, Sungrid UGE, Cadence Virtuoso

rc extraction , routing, Tempus, LVS, Cadence layout tools, Innovus, ERC, STA timing closure, DRC, Placement, Caliber tool, IR EM analysis, block level low power aware floorplanning, tape out activities, Clock Tree Synthesis