Debugging Tools, Pcie, Ethernet, DSP algorithms, clock validation, memory subsystems, fuse controllers, verification methodologies, Simulation Tools, AMBA protocols, microarchitecture concepts, IP Subsystem SoC-level verification, systemverilog, coverage closure, boot flows, security validation flows, random test case development, debugging capabilities for SoC fabric, advanced computer architecture, Performance Analysis

Embedded C, Fpga, C, Spi, DDR, Pcie, Sata, Usb, Uefi, BIOS, Pci, System Architecture, emulation verification, Post Silicon Validation, Memory subsystem, technical debug, Security Protocols, NPU, power management, emulation platforms, SoC IP level Power Management, Validation, low power design, validation strategy, high speed IO, MIPI, Axi, SoC Verification

Embedded C, Fpga, C, Spi, DDR, Pcie, Sata, Usb, BIOS, Uefi, System Architecture, emulation verification, Post Silicon Validation, Memory subsystem, technical debug, Security Protocols, NPU, power management, emulation platforms, SoC IP level Power Management, Validation, low power design, validation strategy, high speed IO peripherals, Axi, MIPI, SoC Verification

Embedded C, Fpga, C, Spi, DDR, Pcie, Sata, Usb, BIOS, Uefi, System Architecture, emulation verification, Post Silicon Validation, Memory subsystem, technical debug, Security Protocols, NPU, power management, emulation platforms, SoC IP level Power Management, Validation, low power design, validation strategy, high speed IO peripherals, Axi, MIPI, SoC Verification

Embedded C, Fpga, C, Spi, DDR, Pcie, Sata, Usb, Uefi, BIOS, System Architecture, emulation verification, Post Silicon Validation, Memory subsystem, technical debug, Security Protocols, NPU, power management, emulation platforms, SoC IP level Power Management, Validation, low power design, validation strategy, high speed IO peripherals, Axi, MIPI, SoC Verification

C/C++ & Python, Debugging Tools, SoC Validation, Display IP, Cross-functional Collaboration, Multimedia Interfaces