Sta, LINT, Synthesis, cdc, DDR families, front-end flows, post-silicon bring-up and debug, micro-architecture development, Rtl Design, FV, Asynchronous interface, Dft, ASIC Design, low-power checks, Low power SoC design, Multi Clock designs

Java, Golang, Python, OpenTelemetry, FinOps, Observability

static timing analysis, Python, Genus Design Compiler, place-and-route Encounter Innovus ICC, high-speed SerDes, physical verification DRC LVS, 3DIC implementation methodologies, DFT methodologies, Asic Physical Design, Verilog RTL, Cadence Virtuoso, RTL Compiler, Clock Tree Synthesis, ASIC synthesis, scripting or programming languages

Linux Administration, Database Administration, PostgreSQL, Prometheus, Elk Stack, Bash, Grafana, Datadog, Jenkins, Devops, Terraform, Ansible, MySQL, Python, AWS, Infrastructure as Code

Lsf, python, Eda, Shell, Linux, Tcl Scripting

Svn, C, Shell, Tcl, Verilog, Python, Perl, Git, systemverilog, Cadence Verisium Manager, Uvm, VHDL, Cadence Xcelium

Rest Api, PowerShell, Python, Javascript, SCA, SIA, Unix Linux systems, LDAP directories, Windows Server OS, Active Directory, Identity WPM, CyberArk Privileged Access Management, CyberArk Privilege Cloud, Credential Provider CP CCP, SWS

Prometheus, Grafana, Datadog, Terraform, Splunk, Helm, Kubernetes, Python, AWS, GitOps, Go, ArgoCD