Logic Design, Verilog, Microprocessors, low power design, LINT, cdc, Design Compiler, Memory controller designs, AMBA protocols, ASIC RTL Design, primetime, Synthesis, Axi, Asynchronous interface, APB, timing concepts for ASIC, RTL Coding, micro-architecture, Multi Clock designs, AHB, System-Verilog

Golang, Apis, Prometheus, Pulumi, Grafana, Datadog, Bash Scripting, Docker, Terraform, Splunk, Kubernetes, Python, Crossplane, Google Cloud Operations, OpenTelemetry

Xcelium, SystemVerilog-RNM, Uvm, Verilog-AMS, Cadence Virtuoso, FineSim, Synopsys VCS, analog mixed signal verification, mixed signal modelling, Spectre

Prometheus, Grafana, Datadog, Terraform, Splunk, Helm, Kubernetes, Python, AWS, GitOps, Go, ArgoCD

Autocad, Catia V5, Wiring harness design, regular expressions, ATIM, VeSyS2.0 wiring harness design tool, Wiring harness testing and inspection, Basic Python scripting, IPC-620 standard, CAD Tools, MENTOR TOOLS

security automation , Servicenow, Json, Iam, Siem, Rest Apis, Python, Email Security, Migrations, Vulnerability Management, Upgrades, Threat Intelligence, Palo Alto XSOAR, XDR, CrowdStrike, EDR, Splunk SOAR, Microsoft Security Technologies, SOAR Architecture, Platform Administration, Enterprise Deployments, SOAR Playbooks, Webhooks

Natural Language Processing (NLP), Retrieval-Augmented Generation (RAG), Large Language Models (LLMs), Machine Learning, Tensorflow, Azure Functions, Pytorch, XGBoost, Visual Studio Code, Python, Azure DevOps, Generative AI, scikit-learn, Azure OpenAI Studio, LightGBM, Azure AI Foundry, Azure AI Services, CI/CD, Streamlit, Azure AI Search, Prompt Engineering

C, Perl, Unix Scripting, Quality Assurance, Python, SPICE Circuit Simulators, Circuit Design, MOSFET Electrical Behavior, Standard Cell Layout Design, Transistor-Level Device Physics, Characterization Modeling, Standard Cell EDA Views, PPA Performance, EDA Tools