Usb, C, Makefile, Windows, Linux, Pcie, Perl, Verilog, Ethernet, Ruby, System Verilog, Systemc, IP level ASIC verification, Graphics pipeline knowledge, UVM testbenches, AXI ACE Protocols, simulation profile efficiency improvement, UVM based verification frameworks, TLM, debugging firmware and RTL code using simulation tools

Jasper, Verilog, System Verilog, Cadence IEV, Synopsys VCS, Synopsys VC-Formal Magellan, Cadence IES, Formal property checking tools, Uvm, Simulation Tools

Verilog, System Verilog, SVA, Synopsys VCS, assertion and coverage-driven verification, Uvm, formal property checking tools, Cadence IES

Jasper, Pcie, Verilog, System Verilog, Synopsys VC-Formal Magellan, formal property checking tools, Uvm, Cadence IEV, Synopsys VCS, HBM, Cadence IES, SVA